// This file is part of www.nand2tetris.org // and the book "The Elements of Computing Systems" // by Nisan and Schocken, MIT Press. // File name: projects/5/CPU.hdl
CHIP CPU {
IN inM[16], // M value input (M = contents of RAM[A]) instruction[16], // Instruction for execution reset; // Signals whether to re-start the current // program (reset==1) or continue executing // the current program (reset==0).
OUT outM[16], // M value output writeM, // Write to M? addressM[15], // Address in data memory (of M) pc[15]; // address of next instruction
PARTS: //// Replace this comment with your code.
//first Mux16 //c=0 instruction //c=1 ALUout Mux16(a= instruction, b= ALUout, sel= instruction[15], out= Mout1);
//because when c=0, A-instruction will set A register to xxx //so when c=0, we need to set load(A) is true Not(in= instruction[15], out= notOp);
//when c=1, we need to focus on ins[5].., so we will get ins[5].. Or(a= instruction[5], b= notOp, out= load0);
//A register Register(in= Mout1, load= load0, out= Aout, out[0..14]= addressM);
//for C-instruction many-bits need calculate //for second Mux16 And(a= instruction[15], b= instruction[12], out= load1);
//for D register And(a= instruction[15], b= instruction[4], out= load2);
//for writeM And(a= instruction[15], b= instruction[3], out= writeM);
//D register Register(in= ALUout, load= load2, out= Dout);
//Second Mux16 Mux16(a= Aout, b= inM, sel= load1, out= Mout2);
//ALU //because when c=0 load2=0,D register makes no change //so we don't need to test c=0 or c=1 then test ins[11..6] ALU(x= Dout, y= Mout2, zx= instruction[11], nx= instruction[10], zy= instruction[9], ny= instruction[8], f= instruction[7], no= instruction[6], out= outM, out= ALUout, zr= Azero, ng= Ang);
//PC Or(a= Azero, b= Ang, out= sym); Not(in= sym, out= Positive);
//out > 0 can JMP And(a= Positive, b= instruction[0], out= isPositive);
//out == 0 can JMP And(a= Azero, b= instruction[1], out= isZero);
//out < 0 can JMP And(a= Ang, b= instruction[2], out= lessZero);
//no condition can JMP And(a= instruction[2], b=instruction[1], out= t12); And(a= instruction[0], b=t12, out= temp);
Or(a= isPositive, b= isZero, out= temp1); Or(a= temp1, b= lessZero, out= temp2); Or(a= temp2, b= temp, out= temp3);
And(a= temp3, b= instruction[15], out= condition); PC(in= Aout, load= condition, inc= true, reset= reset, out[0..14]=pc); }
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